深圳市光华微科技有限公司

74AUP1G74DC,NXP品牌:

The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1G74DC

74AUP1G74DC

74AUP1G74DC

Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • Complies with JEDEC standards: – JESD8-12 (0.8 V to 1.3 V) – JESD8-11 (0.9 V to 1.65 V) – JESD8-7 (1.2 V to 1.95 V) – JESD8-5 (1.8 V to 2.7 V) – JESD8-B (2.7 V to 3.6 V) • ESD protection: – HBM JESD22-A114F Class 3A exceeds 5000 V – MM JESD22-A115-A exceeds 200 V – CDM JESD22-C101E exceeds 1000 V • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78 Class II • Inputs accept voltages up to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial power-down mode operation • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C

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深圳市光华微科技有限公司（简称“光华微”），创建于2016年。是一家混合型电子元件分销商。多年来我们一直本着务实的态度，质量保证而赢得厂商与同行的好评。为国内工程师及采购人员在小量样品测试及采购上带来方便，在价格上有着优势。并为国内多家厂商提供了各种元器件配套服务，与之建立了长期的合作关系，良好的信誉，稳定的供货渠道赢得了众多客户的信赖与支持。我们用人性化的服务与客户一起发展。